The IC 24LC01/24LC02 uses the I2C addressing proto- col and 2-wire serial interface which includes a bidirec- tional serial data bus synchronized by a clock. Microchip 24LC02 EEPROM are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 24LC02 EEPROM. Description, Bit/Bit Serial EePROM Write Protect Memory Chips. Company, Pronics. Datasheet, Download 24LC02 datasheet. Quote. Find where to.
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Functional operation of this device at other conditions beyond datasjeet listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Characteristics Functional Description Timing Diagrams. After receiving the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition.
This happens during the ninth clock cycle.
If not, the chip will return to a standby state. Input Capacitance See Note. A write operation requires an 8-bit data word address following the device address word and acknowledgment. The SDA pin is bidirectional for serial data transfer.
Since dtasheet device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput.
The device is optimized for use in many industrial and com. The device address word consist of a mandatory one, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address.
Data transfer may be initiated only when the. The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing. The microcontroller must terminate the page write sequence with a stop condition.
Write operation with built-in timer. Stresses exceeding the range specified under “Absolute Maxi. Output Capacitance See Note.
ACK polling can be initiated immediately. Internally organized with 8-bit words, the 24l02 requires an 8-bit data word address for random word addressing. Hardware controlled write protection. Instead, after the EEPROM ac- knowledges the receipt of the first data word, the microcontroller can transmit up to seven more data words. Search field Part name Part description.
After this period the first clock pulse is generated. Output Valid from Clock.
Clock and data transition. If the device is still busy with the. For relative timing, refer to timing diagrams. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing. Once the stop condition for a write command has been issued from the master, the device initiates 244lc02 internally timed write cycle.
Time in which the bus must be free before a new transmission can start. During data transfer, the data line must remain stable whenever the clock line is high. Partial page write allowed. Commerical temperature range 0. A page write is initiated the same as byte write, but the microcontroller dstasheet not send a stop condition after the first data word is clocked in.
These three bits must 24lx02 to their corresponding hard-wired input pins. A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low. Data Input Hold Time. Data Input Setup Time. These are stress ratings only. Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit datashedt word.
Serial clock data input.